1. Field of the Invention
The present invention relates to a phase-locked loop circuit.
2. Description of Related Art
FIG. 7 is a block diagram showing a conventional phase-locked loop circuit. In this figure, the reference numeral 1 designates a phase comparator for outputting an error signal corresponding to a phase difference between a reference signal f and an output signal fn; 2 designates a charge pump for outputting a-voltage signal corresponding to the error signal; 3 designates a lowpass filter for passing a low frequency component of the voltage signal; 4 designates a voltage-controlled oscillator for outputting an oscillation frequency corresponding to the voltage signal passing through the lowpass filter 3; and 5 designates a frequency divider for supplying the phase comparator 1 with the output signal fn obtained by dividing the oscillation frequency fed from the voltage-controlled oscillator
FIG. 8 is a circuit diagram showing a configuration of the conventional voltage-controlled oscillator 3. In this figure, the reference numeral 11 designates a controller for outputting a control voltage Vc corresponding to the voltage signal fed from the lowpass filter 3; and 12 designates a voltage-controlled oscillation circuit for outputting the oscillation frequency corresponding to the control voltage Vc.
In the controller 11, the reference numeral 13 designates a DC power supply; 14 designates a P-channel transistor; 15 designates an N-channel transistor; 16 designates a resistor; and 17 designates a ground, which are connected in series. The reference numeral 18 designates an operational amplifier having its non-inverting input terminal connected to the output terminal of the lowpass filter 3, its inverting input terminal to the connecting point between the N-channel transistor 15 and the resistor 16, and its output terminal connected to the gate of the N-channel transistor 15. The gate of the P-channel transistor 14 is connected to the connecting point between the P-channel transistor 14 and the N-channel transistor 15.
Next, the operation of the conventional phase-locked loop circuit will be described.
In FIG. 7, the phase comparator 1 outputs the error signal corresponding to the phase difference between the reference signal f and the output signal fn fed from the frequency divider 5. If the phase of output signal fn lags behind that of the reference signal f, the phase comparator 1 outputs the error signal Up, whereas if the phase of output signal fn leads that of the reference signal f, the phase comparator 1 outputs the error signal Down. The pulse width of each of the error signals Up and Down corresponds to the amount of the phase difference.
The charge pump 2 outputs the voltage signal corresponding to the error signal. The lowpass filter 3 passes only the low frequency component of the voltage signal with eliminating high frequency noise. The voltage-controlled oscillator 4 outputs the oscillation frequency corresponding to the voltage signal fed from the lowpass filter 3.
FIG. 8 shows the voltage-controlled oscillator 4 comprising the controller 11 for outputting the control voltage Vc corresponding to the voltage signal fed from the lowpass filter 3, and the voltage-controlled oscillation circuit 12 for outputting the oscillation frequency corresponding to the control voltage Vc.
The control voltage Vc for controlling the voltage-controlled oscillation circuit 12 is determined by a divided voltage produced by dividing the voltage across the DC power supply 13 to the ground 17 by the resistance RP1 of the P-channel transistor 14 and the resistance RN1 of the N-channel transistor plus the resistance R1 of the resistor 16. The resistance RN1 of the N-channel transistor 15 is varied in response to the potential of the voltage signal supplied from the lowpass filter 3 to the operational amplifier 18. Accordingly, the control voltage Vc varies in response to the potential of the voltage signal supplied from the lowpass filter 3 to the operational amplifier 18.
FIG. 9 is a graph illustrating relationships between the LPF potential (the potential of the output of the lowpass filter) and the oscillation frequency of the conventional voltage-controlled oscillator. In this figure, the oscillation frequency of the voltage-controlled oscillator 4 is locked on f1 when the potential of the voltage signal fed from the lowpass filter 3 is zero, on f2 when the potential of the voltage signal fed from the lowpass filter 3 and the control voltage Vc become equal to each other, and on the locked frequency f0 when the potential of the voltage signal fed from the lowpass filter 3 equals a locked potential V0. Thus, the oscillation frequency of the voltage-controlled oscillator 4 is variable between f1 and f2.
Returning to FIG. 7, the frequency divider 5 divides the oscillation frequency fed from the voltage-controlled oscillator 4, and supplies it to the phase comparator 1 as the output signal fn.
In a locked condition of such a phase-locked loop circuit, if part of the reference signal f supplied to the phase comparator 1 is lost for some reason, the phase comparator 1 makes a decision that the phase of the output signal fn leads that of the reference signal f, thereby outputting the error signal Down.
FIG. 10 is a diagram illustrating a waveform of the error signal Down output from the phase comparator 1 and that of the potential of the voltage signal passing through the lowpass filter 3. As illustrated in this figure, in response to the error signal Down fed from the phase comparator 1, the potential of the voltage signal passing through the lowpass filter 3 transiently drop from the locked potential V0 to Vd. Thus, while the potential of the voltage signal passing through the lowpass filter 3 is varying, the frequency of the output signal fn of the phase-locked loop circuit continues to change.
The characteristics of the phase-locked loop circuit is evaluated in terms of its lock speed and stability. The lock speed refers to the speed at which the phase-locked loop circuit enters the locked condition, and the stability refers to the degree of robustness of the locked condition against disturbance due to noise and the like. The lock speed increases with the amount of change in the potential of the voltage signal passing through the lowpass filter 3, or with the xcex94f/xcex94V in the frequency characteristics of the voltage-controlled oscillator 4. On the other hand, the stability increases with the amount of change in the potential of the voltage signal passing through the lowpass filter 3, or with the xcex94f/xcex94V in the frequency characteristics of the voltage-controlled oscillator 4. In other words, there is a tradeoff between the lock speed and the stability in terms of the amount of change in the potential of the voltage signal passing through the lowpass filter 3.
With the foregoing configuration, the conventional phase-locked loop circuit has a tradeoff between the lock speed and stability concerning the amount of change in the potential of the voltage signal passing through the lowpass filter 3, offering a problem of unable to improved the lock speed and stability at the same time.
The present invention is implemented to solve the foregoing problem. It is therefore an object of the present invention to provide a phase-locked loop circuit capable of improving its lock speed and stability at the same time.
According to one aspect of the present invention, there is provided a phase-locked loop circuit comprising: a phase comparator for outputting an error signal corresponding to a phase difference between a reference signal and an output signal; a charge pump for outputting a voltage signal corresponding to the error signal fed from the phase comparator; a lowpass filter for passing a low frequency component of the voltage signal fed from the charge pump; and a voltage-controlled oscillator including a series circuit having a first transistor, second transistor, a third resistor and a first resistor connected in series in this order, a second resistor connected in parallel with a series connection of the second transistor and the third resistor, and an operational amplifier having its non-inverting input terminal connected to an output terminal of the lowpass filter, its inverting input terminal connected to a connected point of the third resistor and the first resistor, and its output terminal connected to a gate of the second transistor.
Here, the voltage-controlled oscillator may produce the output signal with an oscillation frequency corresponding to a voltage at a connecting point of the first transistor with the second transistor whose resistance is varied by an output of the lowpass filter.
The second resistor and the third resistor may each comprise a plurality of resistors with different resistances, and switches for selecting any of the plurality of resistors.